1. Field of the Invention
The present invention relates to single-switch, three-phase, discontinuous-conduction-mode boost rectifiers. In particular, the present invention relates to such boost rectifiers with input-line-voltage feedforward harmonic-injection control.
2. Description of the Prior Art
Three-phase, discontinuous-conduction-mode (DCM), pulse-width-modulated (PWM) boost rectifiers are often used for three-phase, high-power-factor (HPF) applications, since their input-current waveshape automatically follows the input-voltage waveshape and since they achieve high efficiencies because the reverse-recovery-related losses of the boost diode are eliminated. However, if a DCM, PWM boost rectifier is implemented with conventional low-bandwidth, output-voltage feedback control at a constant switching frequency, which keeps the duty cycle of the switch constant during a rectified line period, the rectifier input current exhibits a relatively large 5.sup.th -order harmonic. As a result, as described in U.S. Pat. No. 5,847,944, to meet the maximum permissible harmonic-current levels defined by the IEC555-2 specification at a power level of 5 kW or above, the 5.sup.th -order harmonic imposes severe design, performance, and cost trade-offs.
To meet the IEC555-2 specifications at power levels above 5 kW, a three-phase, constant-frequency, constant-duty-cycle DCM boost rectifier is designed either with a higher voltage-conversion ratio M (i.e., higher output voltage V.sub.O) or with a control circuit which employs a harmonic-injection technique. Generally, for a given line voltage, a larger M requires a boost switch with a higher voltage rating because of the increased voltage stress. The harmonic-injection approach, however, does not increase the voltage stress of the boost switch, and requires only a few additional components for its implementation. FIG. 1 shows the block diagram of a robust, three-phase DCM boost rectifier, using a simple injection technique developed by Delta Electronics, Inc., which is described in the aforementioned U.S. Pat. No. 5,847,944. Under this technique a voltage signal (V.sub.EA), which is proportional to the inverted AC component of the rectified, three-phase, line-to-line input voltages is injected into the output-voltage feedback loop to vary the duty cycle of the rectifier within a line cycle to reduce the 5.sup.th -order harmonic and improve the total harmonic distortion (THD) of the rectifier input currents.
Various circuit implementations of this injection technique were described in the aforementioned U.S. Pat. No. 5,847,944. An implementation of the harmonic injection circuit 200 and its key waveforms 250-1 to 250-4 are shown in FIGS. 2(a) and 2(b). As shown in FIG. 2(a), the three-phase line voltage, represented by input signals V.sub.a, V.sub.b and V.sub.c at terminals 201-a, 201-b and 201-c, is first rectified by three-phase bridge rectifier 202, and then attenuated by the resistive voltage divider formed by resistors 203 (R.sub.a), 209 (R.sub.a) and 204 (R.sub.b). Phase-to-neutral voltage waveforms and the line-to-line voltage waveforms for V.sub.a, V.sub.b and V.sub.c are shown as waveforms 250-1 and 250-2, respectively. The scaled-down line voltage V.sub.d across resistor 204, which is shown as waveform 250-3 in FIG. 2(b), is then inverted by difference amplifier 206 before filtering by a high-pass filter formed by capacitor 205 (C.sub.b) and resistor 207 (R.sub.h2) to remove the DC component of voltage V.sub.d and to generate injection signal V.sub.inj which is shown as voltage waveform 250-4 in FIG. 2(b). Finally, injection signal V.sub.inj is injected into circuit 100 in FIG. 1 at point A through summing resistor 208 (R.sub.1).
The ratio between the peak-to-peak magnitude of injected signal V.sub.inj(p-p) of FIG. 2(b) and the magnitude of feedback control signal V.sub.EA (i.e., the output voltage of error-amplifier 104 of FIG. 1) defines modulation index m: ##EQU1##
At any given voltage-conversion ratio M, an optimal modulation index m which produces the minimum THD can be determined. FIG. 3 shows, on curve 301, the calculated values of optimal modulation index m for the minimum THD as a function of M. To maximize the input power of the boost rectifier at which the IEC555- 2 specifications are met, the optimal modulation index m is achieved when the ratio of the 7.sup.th -order harmonic and the 5.sup.th -order harmonic is equal to corresponding IEC555-2 limits. Higher-order harmonics, which are easily eliminated by an EMI filter, are not significant in comparison with the 5.sup.th and 7.sup.th -order harmonics. FIG. 3 also shows, on curve 302, the calculated values of optimal modulation index m for achieving maximum input power as a function of M.
Injection circuit 200 of FIG. 2(a) cannot provide a modulation index m which varies with the line voltage (i.e., which varies with M). To implement a harmonic-injection scheme with a variable modulation index, a variable-gain amplifier in the harmonic-injection needs to be added to circuit 200.
Generally, to achieve a low THD, the bandwidth of the output-voltage-feedback control loop of the boost rectifier used in HPF applications is made much less than the line frequency. As a result, the transient response of the control loop to line and load changes is slow, thus causing high transient deviations of the output voltage from the steady-state value. To further explain the effect of a low loop bandwidth on the performance of the converter, FIG. 4 shows a block diagram of a conventional output-voltage-feedback control circuit 400 for a power stage 450 connected to an input voltage source 412 (V.sub.IN). Control circuit 400 includes error amplifier (EA) 401, PWM modulator 402, a signal generator providing a constant-frequency, sawtooth ramp voltage signal (V.sub.RAMP) at terminal 403, a signal generator 404 providing a reference voltage (V.sub.REF), and a voltage divider including resistors 405 (R.sub.3) and 406 (R.sub.4). In FIG. 4, the divider of resistors 405 and 406 scales down output voltage V.sub.O for comparison with reference voltage V.sub.REF in error amplifier 401. The voltage V.sub.EA at the output terminal 407 of error amplifier 401 is proportional to the voltage difference between the scaled output voltage at terminal 408 and reference voltage V.sub.REF. Voltage V.sub.EA is then compared to the sawtooth ramp voltage V.sub.RAMP at PWM modulator 402 to generate a switch control signal V.sub.Switch with the desirable duty cycle to drive switch 103 of FIG. 1. Because of the negative feedback in the output voltage feedback control loop (T.sub.V), error-amplifier output voltage V.sub.EA maintains output voltage V.sub.O substantially constant by appropriately modulating the duty cycle of switch control signal V.sub.Switch. Compensation impedances 411 (Z.sub.1) and 410 (Z.sub.2) of error amplifier 401 provides an appropriate gain, bandwidth, and frequency compensation to maintain circuit 400 stable for all operating conditions.
FIG. 5 shows the transient responses of voltage V.sub.O, voltages V.sub.EA and V.sub.RAMP, and switch control signal V.sub.Gate (i.e., waveforms 502, 503, 504 and 505) of circuit shown in FIG. 4 with a low-bandwidth output-voltage-feedback control circuit 400 in response to a positive step line-voltage increase .DELTA.V.sub.IN at time t=T.sub.O. However, because of slow response of control circuit 400, voltage V.sub.EA changes slowly, so that the duty cycle of switch control signal V.sub.GATE also changes slowly. Consequently, a high transient overshoot in output voltage V.sub.O is seen. Because of such an overshoot, power-stage semiconductor components with a higher voltage rating, hence more expensive and more lossy, are usually required to maintain the necessary design margin between the maximum voltage stress of the components and their voltage rating.
To reduce the above transient output-voltage overshoot caused by a change in the input voltage, a feedforward control technique (illustrated by feedforward circuit 600 of FIG. 6) is developed to provide a faster response in control circuit 400 to input voltage changes. Using feedforward control circuit 600, instead of a fixed-slope sawtooth ramp, the input signal (i.e., voltage V.sub.RAMP) of PWM modulator 402 is a variable slope ramp that is proportional to input voltage V.sub.IN. Input voltage V.sub.IN is first sensed and attenuated by the voltage divider formed by resistors 601 (R.sub.1) and 602 (R.sub.2) and then inverted by inverting circuit 603, before being integrated by integrator circuit 604. Integrator circuit 604 is reset at the beginning of each switching cycle by an external, fixed-frequency clock signal on terminal 605.
Because of feedforward control circuit 600, the duty cycle of switch control signal V.sub.Gate is determined by the voltage V.sub.EA of error amplifier 401 and the input-voltage dependent V.sub.RAMP provided by integrator circuit 604. Thus, a change in input voltage V.sub.IN causes, within one switching cycle, a change in the duty cycle of switch control signal V.sub.Gate , even while the bandwidth of control circuit 400 remains low (i.e., voltage V.sub.EA changes slowly). FIG. 7 shows the transient responses of voltage V.sub.O voltage V.sub.EA and voltage V.sub.RAMP, and switch control signal V.sub.Gate (i.e., waveforms 702, 703, 704 and 705 ) of the circuit in FIG. 6 with a low-bandwidth output-voltage-feedback control circuit 400 and feedforward circuit 600, in response to a positive step line-voltage increase .DELTA.V.sub.IN at time t=T.sub.O (waveform 701 ). In FIG. 7, after input voltage V.sub.IN is increased at time t=T.sub.O, the slope of voltage V.sub.RAMP increases, so that the duty cycle of switch control signal V.sub.Gate decreases immediately to reduce any overshoot in output voltage V.sub.O. As shown in FIG. 7, the response of voltage V.sub.EA of error amplifier 401 remains slow, since the bandwidth of control circuit 400 remains unchanged.